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Silicon Labs /SiM3_NRND /SIM3U166_B /I2S_0 /DBGCONTROL

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Interpret as DBGCONTROL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)TXDBGHEN 0 (DISABLED)RXDBGHEN 0 (RUN)TXDBGMD 0 (RUN)RXDBGMD

RXDBGHEN=DISABLED, TXDBGMD=RUN, RXDBGMD=RUN, TXDBGHEN=DISABLED

Description

Debug Control

Fields

TXDBGHEN

I2S Transmit DMA Debug Halt Enable.

0 (DISABLED): Transmit DMA requests continue while the core is debug mode.

1 (ENABLED): Transmit DMA requests stop while the core is debug mode.
RXDBGHEN

I2S Receive DMA Debug Halt Enable.

0 (DISABLED): Receive DMA requests continue while the core is debug mode.

1 (ENABLED): Receive DMA requests stop while the core is debug mode.
TXDBGMD

I2S Transmit Debug Mode.

0 (RUN): The clock to the I2S transmitter is active in debug mode.

1 (HALT): The clock to the I2S transmitter is not active in debug mode. The clock divider keeps running and the clock will be disabled when two samples are ready to be sent by the transmitter.
RXDBGMD

I2S Receive Debug Mode.

0 (RUN): The clock to the I2S receiver is active in debug mode.

1 (HALT): The clock to the I2S receiver is not active in debug mode. The clock divider keeps running and the clock will be disabled when two samples are captured in the receiver.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data